Reference-Free CMOS Pipeline Analog-to-Digital Converters by Michael Figueiredo João Goes & Guiomar Evans

Author:Michael Figueiredo, João Goes & Guiomar Evans
Language: eng
Format: epub
Publisher: Springer New York, New York, NY

Fig. 4.11Proof-of-functionality of a 7-bit 500 MS/s pipeline ADC employing the proposed quantizer in all pipelined stages: a 8192-point FFT. b DNL and INL

Figure 4.11 shows the electrically simulated 8192-point FFT, DNL and INL results of the pipeline ADC for a 200 MHz input signal. A SFDR of 45.5 dB and an SNDR of 41.4 dB is obtained which leads to an ENOB of 6.6 dB. Concerning DNL and INL, the maximum absolute values obtained are 0.32 and 0.59 LSBs respectively. These results demonstrate the practical usefulness of the proposed 1.5-bit flash quantizer circuit since good DNL, INL, and SNDR performance are achieved.

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